UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 406

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark m = 02 to 07
404
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMR00 and TMRm registers of each channel to
be used (determines operation mode of channels).
An interval (period) value is set to the TDR00 register of
the master channel, and a duty factor is set to the
TDRm register of slave channels 2 to 7.
Sets slave channels 2 to 7.
Sets TOEm (slaves 2 to 7) to 1 (only when operation is
resumed).
The TS00 (master) and TSm (slaves 2 to 7) bits of the
TS0 register are set to 1 at the same time.
Set values of the TDR00 and TDRm registers can be
changed after INTTM00 of the master channel is
generated.
The TCR00 and TCRm registers can always be read.
Set values of the TOL0, TO0, and TOE0 registers can
be changed.
Determines clock frequencies of CK00 and CK01.
Sets the TOMm bit to 1 (slave channel output mode).
Sets the TOTm bit to 0 (generates other than
triangular wave PWM output).
Sets the TOLm bit and determines the active level of
the TOm output.
Sets the TOm bit and determines default level of the
TOm output.
Sets the TOEm bit to 1 and enables operation of
TOm.
Clears the port register and port mode register to 0.
The TS00 and TSm bits automatically return to 0
because they are trigger bits.
Figure 7-27. Operation Procedure When 6-Phase PWM Output Function Is Used (1/2)
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOm pin goes into Hi-Z output state.
The TOm default setting level is output when the port mode
register is in output mode and the port register is 0.
TOm does not change because channel has stopped
operating.
The TOm pin outputs the TOm set level.
TE00 = 1, TEm = 1
The counter of the master channel loads the TDR00 value to
TCR00 and counts down. When the count value reaches
TCR00 = 0000H, INTTM00 is generated. At the same time,
the value of the TDR00 register is loaded to TCR00, and the
counter starts counting down again.
At slave channels 2 to 7, the values of the TDRm register
are transferred to TCRm, triggered by INTTM00 of the
master channel, and the counter starts counting down. The
output levels of TOm become active one count clock after
generation of the INTTM00 output from the master channel.
It becomes inactive when TCRm = 0000H, and the counting
operation is stopped. After that, the above operation is
repeated.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
When the master channel starts counting, INTTM00 is
generated. Triggered by this interrupt, the slave channels
2 to 7 also start counting.
Hardware Status