UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 612

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

610
(when UART0: RxD0)
(when CSI01: SCK01)
(when CSI10: SCK10)
(when CSI00: SCK00)
(when UART1: R
(when IIC10: SDA10)
(when IIC10: SCL10)
Figure 13-2. Block Diagram of Serial Array Unit (44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3 and
Serial data input pin
Serial data input pin
Serial data input pin
(when CSI00: SI00)
(when CSI01: SI01)
(when CSI10: SI10)
Serial clock I/O pin
Serial clock I/O pin
Serial clock I/O pin
INTTM02
When UART0
When UART1
X
D1)
f
CLK
Peripheral enable
register 0 (PER0)
SAU0EN
(LIN-bus supported)
SNFEN00
elimination
(LIN-bus supported)
SNFEN10
enabled/
disabled
TXE
Channel 2
Channel 3
Noise
elimination
00
Selector
enabled/
disabled
Noise
Channel 0
PM75
Channel 1
RXE
00
PRS
013
detection
Edge
DAP
00
PRS
012
Edge/level
detection
Edge/level
Edge/level
Edge/level
CK01
detection
detection
detection
4
CK01
CK01
Serial clock select register 0 (SPS0)
CK01
Output latch
Selector
0
CKP
PRS
(P75)
00
011
Serial communication operation setting register 00 (SCR00)
f
SCK
f
CLK
0
EOC
/2
CK00
00
PRS
010
Prescaler
0
CK00
CK00
to f
CK00
CLK
0
CKS00
PTC
001
PRS
CHAPTER 13 SERIAL ARRAY UNIT
003
/2
Serial mode register 00 (SMR00)
11
f
MCK
0
CCS00 STS00 MD002
PTC
Selector
000
PRS
002
(Clock division setting block)
User’s Manual U19678EJ1V1UD
4
f
CLK
1
DIR
00
PRS
/2
001
0
to f
CKO02 CKO01 CKO00
CLK
Serial data register 00 (SDR00)
SLC
001
78K0R/IE3)
PRS
000
/2
11
Serial output register 0 (SO0)
MD001
SLC
000
f
TCLK
DLS
002
(Buffer register block)
0
DLS
001
Shift register
Communication controller
Communication controller
Communication controller
Communication controller
0
(for transmission)
CSI00 or UART0
(for transmission)
DLS
Mode selection
000
Mode selection
CSI10 or IIC10
Mode selection
CSI01 or UART0
Mode selection
(for reception)
(for reception)
or UART1
UART1
0
TSF
00
Serial status register 00 (SSR00)
0
BFF
00
SE03 SE02 SE01
SS03 SS02 SS01
ST03
1
0
0
Output latch
FECT
FEF
SOL02
Serial flag clear trigger
register 00 (SIR00)
SOE02 SOE01 SOE00
00
SO02 SO01
00
ST02 ST01
(P73)
Error controller
Error controller
Error controller
PECT
controller
controller
PEF
Interrupt
Output
00
00
0
OVCT
OVF
SOL00
00
SO00
00
SE00
SS00
ST00
information
Clear
PM73
Error
Serial channel enable
status register 0 (SE0)
Serial channel stop
register 0 (ST0)
Serial channel start
register 0 (SS0)
Serial output enable
register 0 (SOE0)
Serial output level
register 0 (SOL0)
Noise filter enable
register 0 (NFEN0)
SNFEN
10
Serial transfer end interrupt
(when UART1: INTSR1)
Serial transfer error interrupt
(INTSRE1)
Serial data output pin
(when CSI00: SO00)
(when UART0: T
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Serial data output pin
(when CSI01: SO01)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Serial transfer error interrupt
(INTSRE0)
Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: T
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
SNFEN
00
X
X
D0)
D1)