UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 340

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
338
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAUS
stop
Figure 6-55. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)
Sets the TAU0EN bit of the PER2 register to 1.
Sets the TPS0 register.
Sets the TMRn register (determines operation mode of
channel).
Clears TOEn to 0 and stops operation of TOn.
Sets the TSn bit to 1.
Detects TIn pin input count start valid edge.
Set value of the TDRn register can be changed.
The TCRn register can always be read.
The TSRn register is not used.
Set values of TMRn register, TOMn, TOLn, TOn, and
TOEn bits cannot be changed.
The TTn bit is set to 1.
The TAU0EN bit of PER2 register is cleared to 0.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
The TSn bit automatically returns to 0 because it is a
trigger bit.
TTn bit automatically returns to 0 because it is a trigger
bit.
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEn = 1, and the TIn pin start edge detection wait status is
set.
Clears TCRn to 0000H and starts counting up.
When the TIn pin start edge is detected, the counter
(TCRn) counts up from 0000H. If a capture edge of the
TIn pin is detected, the count value is transferred to TDRn
and INTTMn is generated.
If an overflow occurs at this time, the OVF bit of the TSRn
register is set; if an overflow does not occur, the OVF bit is
cleared. TCRn stops the count operation until the next
TIn pin start edge is detected.
After that, the above operation is repeated.
TEn = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
TCRn holds count value and stops.
The OVF bit of the TSRn register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
Hardware Status