UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 685

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
Changing setting of SPS0 register
Changing setting of SMR0n register
Changing setting of SCR0n register
Manipulating target for communication
Starting setting for resumption
Starting communication
Figure 13-59. Procedure for Resuming Slave Reception
Writing to SS0 register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
Stop the target for communication or wait
until the target completes its operation.
Disable clock output of the target
channel by setting a port register and a
port mode register.
Re-set the register to change the
operation clock setting.
Re-set the register to change the serial
mode register 0n (SMR0n) setting.
Re-set the register to change the serial
communication operation setting register
0n (SCR0n) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SS0n bit of the target channel to 1
and set SE0n bit to 1 (to enable operation).
Wait for a clock from the master.
trigger register 0n (SIR0n).
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