UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 288

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

286
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
(4) Timer status register n (TSRn)
Symbol
TSRn
TSRn indicates the overflow status of the counter of channel n.
TSRn is valid only in the capture mode (MDn4 to MDn1 = 0010B) and capture & one-count mode (MDn4 to
MDn1 = 0110B). It will not be set in any other mode.
Furthermore, CSF is valid only in the up and down count mode (MDn4 to MDn1 = 1001B)
in any other mode.
See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear conditions.
TSRn can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears TSRn to 0000H.
Notes 1. This operation mode or bit is used with the inverter control function. For the inverter control
Note These operation modes are used with the inverter control function. For details, refer to CHAPTER 7
Remark
F01D0H, F01D1H (TSR08) to F01D6H, F01D7H (TSR11)
Notes 1, 2
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
• Up and down count mode
CSF
OVF
2. Channel 0, which does not have a higher channel, is always fixed to “0”, because CSF is generated
INVERTER CONTROL FUNCTIONS.
15
0
1
0
1
0
Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
function, refer to CHAPTER 7 INVERTER CONTROL FUNCTIONS.
based on the up/down signal of the higher master channel.
Timer operation mode
Indicates that the count clock is counting up.
Indicates that the count clock is counting down.
Overflow does not occur.
Overflow occurs.
14
0
13
0
Figure 6-8. Format of Timer Status Register n (TSRn)
12
0
Note
CHAPTER 6 TIMER ARRAY UNIT TAUS
11
0
clear
set
clear
set
OVF
(capture mode and capture & one-count mode only)
User’s Manual U19678EJ1V1UD
10
0
Count-up or count-down status of count clock
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
Counter overflow status of channel n
(up and down count mode only)
9
0
8
0
After reset: 0000H
(Use prohibited, not set and not cleared)
7
0
6
0
Set/clear conditions
5
0
R
−
4
0
3
0
Note 1
. It will not be set
2
0
Notes 1, 2
CSF
1
OVF
0