UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 702

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6.1 UART transmission
stop synchronization).
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
700
Remarks 1. f
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
UART transmission is an operation to transmit data from the 78K0R/Ix3 to another device asynchronously (start-
Of two channels used for UART, the even channel is used for UART transmission.
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS ).
UART
2. n:
f
MCK
CLK
:
:
Operation clock frequency of target channel
System clock frequency
Channel number (n = 0, 2)
Channel 0 of SAU
TxD0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
None
5, 7, or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
/6 [bps] (SDR0n [15:9] = 2 or more), Min. f
CHAPTER 13 SERIAL ARRAY UNIT
UART0
User’s Manual U19678EJ1V1UD
CLK
Channel 2 of SAU
TxD1
INTST1
/(2 × 2
11
× 128) [bps]
UART1
Note