UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 613

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Shift register
(2) Lower 8 bits of the serial data register 0n (SDR0n)
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register 0n (SDR0n).
SDR0n register can be read or written in 16-bit units.
The lower 8 bits of SDR0n register can be read or written
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IIC10 communication … SIO10 (IIC10 data register)
Reset signal generation clears SDR0n register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
SDR0n register is the transmit/receive data register (16 bits) of channel n.
transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the
operation clock (f
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is
to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (DLS0n0
to DLS0n2) of the serial communication operation setting register 0n (SCR0n), regardless of the output
sequence of the data.
• 5-bit data length (stored in bits 0 to 4 of SDR0n register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDR0n register)
• 8-bit data length (stored in bits 0 to 7 of SDR0n register)
2. n: Channel number (n = 0 to 3),
pin and 48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only) ),
q: UART number (q = 0, 1)
p: CSI number (p = 10 (78K0R/IB3 and 38-pin products of 78K0R/IC3), p = 00, 01 and 10 (44-
MCK
).
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
Shift register
7
Note
6
as the following SFR, depending on the
Note Writing in 8-bit units is prohibited
5
when the operation is stopped
(SE0n = 0).
4
Bits 7 to 0 function as a
3
2
1
0
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