UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 99

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.1 Memory Space
Products in the 78K0R/Ix3 can access a 1 MB memory space. Figures 3-1 to 3-4 show the memory maps.
Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function. Since this
Data memory
space
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Program
Setting).
memory
When boot swap is used:
area is used for self-programming library.
space
F F F F F H
F F F 0 0 H
F F B 0 0 H
F F A F F H
F 4 0 0 0 H
F 3 F F F H
F 1 0 0 0 H
F 0 F F F H
F 0 8 0 0 H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
0 4 0 0 0 H
0 3 F F F H
F F E F F H
F F E E 0 H
F F E D F H
0 0 0 0 0 H
Special function register (2nd SFR)
General-purpose register
Special function register (SFR)
Figure 3-1. Memory Map (
32 bytes
Flash memory
RAM
CHAPTER 3 CPU ARCHITECTURE
Reserved
Reserved
256 bytes
Reserved
Mirror
12 KB
16 KB
1 KB
2 KB
Notes 1, 2
security IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
User’s Manual U19678EJ1V1UD
μ
PD78F1201, 78F1211)
0 0 0 C E H
0 0 0 C D H
0 0 0 8 0 H
0 0 0 7 F H
0 3 F F F H
0 1 0 C E H
0 1 0 C D H
0 1 0 C 4 H
0 1 0 C 3 H
0 1 0 C 0 H
0 1 0 B F H
0 1 0 8 0 H
0 1 0 7 F H
0 1 0 0 0 H
0 0 F F F H
0 0 0 C 4 H
0 0 0 C 3 H
0 0 0 C 0 H
0 0 0 B F H
0 0 0 0 0 H
On-chip debug security
On-chip debug security
Option byte area
Option byte area
ID setting area
ID setting area
CALLT table area
CALLT table area
Vector table area
Vector table area
Program area
Program area
128 bytes
128 bytes
64 bytes
64 bytes
10 bytes
10 bytes
4 bytes
4 bytes
Note 3
Note 3
Note 3
Note 3
0 1 F F F H
Boot cluster 0
Boot cluster 1
Note 4
Security
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