UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 545

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UPD78F1233GB-GAH-AX

Manufacturer Part Number
UPD78F1233GB-GAH-AX
Description
MCU 16BIT 78K0R/LX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1233GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1233GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Address: F00F0H
(1) Peripheral enable register 0 (PER0)
(2) Real-time counter control register 0 (RTCC0)
Symbol
PER0
PER0 is used to enable or disable supplying the clock to the peripheral hardware macro. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the real-time counter is used, be sure to set bit 7 (RTCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
The RTCC0 register is an 8-bit register that is used to start or stop the real-time counter operation, and set a
12- or 24-hour system and the constant-period interrupt function.
RTCC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
RTCEN
RTCEN
Notes 1. IICAEN bit is not provided in the 78K0R/IB3 and the 38-pin and 44 pin products of the
Cautions 1. When using the real-time counter, first set RTCEN to 1, while oscillation of the
<7>
0
1
After reset: 00H
2. RTCEN is used to supply or stop the clock used when accessing the real-time counter
(RTC) register from the CPU. RTCEN cannot control supply of the operating clock (f
RTC.
Stops input clock supply.
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
Enables input clock supply.
• SFR used by the real-time counter (RTC) can be read/written.
78K0R/IC3. In the 78K0R/IB3 and the 38-pin and 44 pin products of the 78K0R/IC3, bit 4
of PER0 register is fixed to 0.
2. Be sure to clear bits 0, 1, 3, and 6 (78K0R/IB3 and 38-pin and 44-pin products of
Figure 9-2. Format of Peripheral Enable Register 0 (PER0)
subsystem clock (f
real-time counter is ignored, and, even if the register is read, only the default
value is read.
the 78K0R/IC3: 0, 1, 3, 4 and 6) of PER0 register to 0.
6
0
R/W
CHAPTER 9 REAL-TIME COUNTER
ADCEN
<5>
User’s Manual U19678EJ1V1UD
Control of real-time counter (RTC) input clock
SUB
IICAEN
) is stable. If RTCEN = 0, writing to a control register of the
<4>
Note 1
3
0
SAU0EN
<2>
Note 2
1
0
0
0
SUB
543
) to

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