UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 926

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

924
(when X1 oscillation
oscillation clock (f
Internal high-speed
V
V
Internal reset signal
system clock (f
POR
PDR
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 21
Remark V
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
2.7 V
CPU
2.
3.
4.
5.
6.
(V
MX
V
Note 1
IH
Operation
LVI
)
)
DD
LOW-VOLTAGE DETECTOR).
V
V
Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
stops
The operation guaranteed range is 2.7 V ≤ V
the supply voltage has become at least 2.7 V. To make the state at lower than 2.7 V reset state when
the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
Set so that no more than 3.6 ms elapses between when power is applied and when the voltage
reaches 2.7 V. If more time is required (if the voltage needs to rise more slowly than the 0.5 V/ms
(MIN.) rating), be sure to input a low level to the RESET pin before the voltage reaches 2.7 V after
power application(For supply voltage rise time timing and power supply voltage rise inclination, see
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
The reset processing time, such as when waiting for internal voltage stabilization, includes the
oscillation accuracy stabilization time of the internal high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock
lapse of the stabilization time.
The 78K0R/IB3 doesn’t have the subsystem clock (XT clock).
LVI
POR
PDR
:
: POC power supply rise detection voltage
: POC power supply fall detection voltage
0.5 V/ms (MIN.)
LVI detection voltage
Wait for oscillation
accuracy stabilization
Reset processing
3.6 ms (MAX.)
specified by software
Starting oscillation is
(about 2.1 to
5.8 ms)
Note 2
Note 2
used for reset
Set LVI to be
Note 3
oscillation clock)
(internal high-speed
Normal operation
CHAPTER 20 POWER-ON-CLEAR CIRCUIT
Note 5
and Low-Voltage Detector
User’s Manual U19678EJ1V1UD
(oscillation
Reset processing (about 195 to 341 s)
Reset
period
stop)
Wait for oscillation
accuracy stabilization
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software
Starting oscillation is
DD
≤ 5.5 V. Make sure to perform normal operation after
Note 4
Note 5
Note 6
μ
, use the timer function for confirmation of the
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Reset processing
Starting oscillation is
specified by software
(about 2.1 to
5.8 ms)
used for reset
Set LVI to be
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 5
Note 6
Operation stops
can be