UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 513

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
Operation
start
During
operation
Operation
stop
TAUS
stop
Figure 7-99. Operation Procedure When Complementary Modulation Output Function Is Used (2/2)
p = 02, 04, 06
q = 03, 05, 07
Sets TOE00 (master), TOEp and TOEq (slaves 2 to 7)
to 1 (only when operation is resumed).
The TS00 (master), TS01 (slave 1), TSp and TSq
(slaves 2 to 7) bits of the TS0 register are set to 1 at the
same time.
The set value of the TDR00 (master) register must be
changed during an up status period.
The set value of the TDRp and TDRq (slaves 2 to 7)
register can be changed.
The TCR00, TCR01, TCRp, and TCRq registers can
always be read.
Set values of the TOLp, TOLq, TROp, TROq, TMEp,
and TMEq registers can be changed.
The TT00 (master), TT01 (slave 1), TTp, and TTq
(slaves 2 to 7) bits are set to 1 at the same time.
Sets the TOE00 (master), TOEp and TOEq (slaves 2 to
7) bits to 0, TO00, TOp, and TOq bits to value.
To hold the TO00, TOp, and TOq pins output level
When holding the TO00, TOp, and TOq pins output level
is not necessary
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
The TS00, TS01, TSp and TSq bits automatically
return to 0 because they are trigger bits.
The TT00, TT01, TTp, and TTq bits automatically
return to 0 because they are trigger bits.
Clears the TO00, TOp, and TOq bits to 0 after the
value to be held is set to the port register.
Switches the port mode register to input mode.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
The TO00, TOp, and TOq pins output the TO00, TOp, and
TOq set level.
TE00 = 1, TE01 = 1, TEp = 1, TEq = 1
6-Phase triangular wave PWM output is performed by the
master channel and slave channels 2 to 7.
At slave channel 1, the values of the TDR01 register are
transferred to TCR01, triggered by INTTM00 of the master
channel, and the counter starts counting down.
Slave channels 2 to 7 perform real-time output by using the
INTTM01 signal of slave channel 1. Complementary
modulation output of the PWM and real-time outputs is
performed according to setting of TMEp and TMEq.
After that, the above operation is repeated.
TE00, TE01, TEp, TEq = 0, and count operation stops.
The TO00, TOp, and TOq pins output level is held by port
function.
The TO00, TOp, and TOq pins output level goes into Hi-Z
output state.
Power-off status
When the master channel starts counting, INTTM00 is
generated. Triggered by this interrupt, the slave channels
1 also start counting.
TCR00 TCR01, TCRp, and TCRq hold count value and stops.
The TO00, TOp, and TOq output is not initialized but holds
current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00, TOp, and TOq bits are cleared to 0 and the
TO00, TOp, and TOq pins are set to port mode.)
Hardware Status
511