UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 592

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter
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<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D
<2> Set the A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM, and set the operation
<3> Set bit 0 (ADCE) of A/D converter mode register (ADM) to 1 to start the operation of the A/D voltage
<4> Set the channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and
<5> Set the programmable gain amplifier operation to set the programmable gain amplifier output signal from
<6> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<7> Use the A/D converter mode register 1 (ADM1) to set the trigger mode.
<8> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
<9> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<10> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<11> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
<12> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
<13> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
<14> Comparison is continued in this way up to bit 0 of SAR.
<15> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<16> Repeat steps <9> to <15>, until ADCS is cleared to 0.
Caution Make sure the period of <3> to <8> is 1
converter.
mode by using bit 6 (ADMD) of ADM.
comparator.
set to input mode by using port mode registers (PM2, PM8, and PM15).
PGAI pin (PGAO) for the analog input channel (refer to 8.4.1 Starting comparator and programmable gain
amplifier operation).
A timer trigger wait state is entered if the timer trigger mode is set in step <7>.
(<9> to <15> are operations performed by hardware.)
sampled voltage is held until the A/D conversion operation has ended.
(1/2) AV
voltage comparator. If the analog input is greater than (1/2) AV
analog input is smaller than (1/2) AV
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Sampled voltage ≥ Voltage tap: Bit 8 = 1
• Sampled voltage < Voltage tap: Bit 8 = 0
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <8>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
start from <6>.
REF
by the tap selector.
REF
REF
CHAPTER 12 A/D CONVERTER
REF
User’s Manual U19678EJ1V1UD
μ
, the MSB is reset to 0.
s or longer, and start <8>. To change a channel of A/D conversion,
μ
s or more.
REF
, the MSB of SAR remains set to 1. If the