UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 867

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Operation in standby mode
(5) Operation if address in general-purpose register area or other than those of internal RAM area is
(4) DMA pending instruction
The DMA controller operates as follows in the standby mode.
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
• CALL
• CALL
• CALL
• CALL
• CALLT
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H,
specified
The address indicated by DRA0n is incremented during DMA transfer. If the address is incremented to an
address in the general-purpose register area or exceeds the area of the internal RAM, the following operation
is performed.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that
the address is within the internal RAM area other than the general-purpose register area.
MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H and PSW each, and 8-bit manipulation instructions with operands including ES registers
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
HALT mode
STOP mode
Status
!addr16
&!addr16
!!addr20
rp
[addr5]
F F F 0 0 H
FFEFFH
FFEE0H
FFEDFH
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
Table 16-3. DMA Operation in Standby Mode
CHAPTER 16 DMA CONTROLLER
General-purpose registers
User’s Manual U19678EJ1V1UD
Internal RAM
DMA Operation
DMA transfer enabled area
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