UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 703

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Register setting
SMR0n
SCR0n
SDR0n
SOL0
(a) Serial mode register 0n (SMR0n)
(b) Serial communication operation setting register 0n (SCR0n)
(d) Serial output level register 0 (SOL0) … Sets only the bits of the target channel.
Remark
(c) Serial data register 0n (SDR0n) (lower 8 bits: TXDq)
TXE0n
CKS0n
0/1
Operation clock (f
0: Prescaler output clock CK00 set by SPS0 register
1: Prescaler output clock CK01 set by SPS0 register
15
15
15
15
1
0
Figure 13-71. Example of Contents of Registers for UART Transmission of UART
Setting of parity bit
00B: No parity
01B: Appending 0 parity
10B: Appending Even parity
11B: Appending Odd parity
n: Channel number (n = 0, 2), q: UART number (q = 0, 1)
0/1: Set to 0 or 1 depending on the usage of the user
RXE0n
CCS0n
14
14
14
14
0
0
0
: Setting is fixed in the UART transmission mode,
DAP0n
13
13
13
13
0
0
0
Baud rate setting
MCK
CKP0n
12
12
) of channel n
12
12
0
0
0
11
11
11
11
0
0
0
CHAPTER 13 SERIAL ARRAY UNIT
EOC0n
10
10
10
10
0
0
0
User’s Manual U19678EJ1V1UD
(UART0, UART1) (1/2)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
PTC0n1
0/1
9
9
0
0
9
9
PTC0n0
STS0n
0/1
8
8
0
8
0
8
0
0: Forward (normal) transmission
DIR0n
0/1
0
7
7
7
7
0
SIS0n0
1: Reverse transmission
0
0
6
6
6
6
0
: Setting disabled (fixed by hardware)
SLC0n1
0/1
1
5
5
0
5
5
Transmit data setting
SLC0n0
0/1
4
0
4
0
4
4
TXDq
Interrupt source of channel n
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
3
0
3
0
0
3
3
1: Buffer empty interrupt
0: Transfer end interrupt
MD0n2
DLS0n2
SOL02
0/1
2
0
2
1
2
2
MD0n1
DLS0n1
0/1
1
1
1
1
1
0
MD0n0
DLS0n0
SOL00
0/1
0/1
0/1
0
0
0
0
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