UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 233

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remark f
f
f
f
f
f
f
f
The fastest instruction can be executed in 1 clock of the CPU clock in the 78K0R/Ix3. Therefore, the relationship
between the CPU clock (f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
(Value set by the
MDIV2 to MDIV0
/2
CPU Clock
/2
/2
/2
/2
/2
2
3
4
5
bits)
2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
f
MAIN
SUB
The 78K0R/IB3 doesn’t have the subsystem clock.
f
this case, f
register to 1.
MAIN
Cautions 1. Be sure to set bit 3 to 1.
: Subsystem clock frequency
: Main system clock frequency (f
at 40 MHz can be used as f
0.1
0.2
0.4
0.8
1.6
3.2
At 10 MHz
Operation
μ
μ
μ
μ
μ
μ
High-Speed System Clock
CLK
2. The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
3. If the peripheral hardware clock is used as the subsystem clock, the operations
s
s
s
s
s
s
/2 (20 MHz) is specified for the CPU clock by setting the DSPO bit of the DSCCTL
CLK
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, clock output/buzzer output,
and watchdog timer) is also changed at the same time. Consequently, stop each
peripheral function when changing the CPU/peripheral operating hardware clock.
of the A/D converter and IICA are not guaranteed.
characteristics of the peripheral hardware, refer to the chapters describing the
various
SPECIFICATIONS.
) and the minimum instruction execution time is as shown in Table 5-2.
(MCM0 = 1)
−
0.05
0.1
0.2
0.4
0.8
1.6
peripheral
CHAPTER 5 CLOCK GENERATOR
Main System Clock (CSS = 0)
At 20 MHz
Operation
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
User’s Manual U19678EJ1V1UD
CLK
Minimum Instruction Execution Time: 1/f
IH,
only for the timer array unit TAUS and controlling the inverter. In
f
IH40
hardware
0.125
0.25
(default)
0.5
1.0
2.0
4.0
At 8 MHz (TYP.)
or f
Internal High-Speed Oscillation
Operation
μ
μ
μ
μ
MX
μ
s (TYP.)
s (TYP.)
s (TYP.)
s (TYP.)
μ
s (TYP.)
)
s (TYP.)
Clock (MCM0 = 0)
as
well
−
0.1
0.2
0.4
0.8
(TYP.) Operation
0.05
Note 2
0.05
At 40 MHz
μ
μ
μ
μ
as
μ
μ
s (TYP.)
s (TYP.)
s (TYP.)
s (TYP.)
s (TYP.)
s (TYP.)
CHAPTER
CLK
61
Subsystem Clock
μ
s
At 32.768 kHz
28
For the operating
(CSS = 1)
Operation
−
−
−
−
−
−
ELECTRICAL
Note 1
231