UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 457

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UPD78F1233GB-GAH-AX

Manufacturer Part Number
UPD78F1233GB-GAH-AX
Description
MCU 16BIT 78K0R/LX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1233GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1233GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(a) Timer mode register n (TMRn) of slave channel 1 (real-time output trigger generation channel
(b) Other registers of slave channel 1 (real-time output trigger generation channel (TRCn = 1))
TMRn
(TRCn = 1))
Remark
CKSn
TRO0:TROn
TOE0:TOEn
TO0:TOn
TOM0:TOMn
TOT0:TOTn
TOL0:TOLn
TDE0:TDEn
TRE0:TREn
TRC0:TRCn
TME0:TMEn
15
0
When Linked Real-Time Output Function (Type 1) (Slave Channel 1) Is Used
Operation clock selection
14
0: Selects CK00 as operation clock of channel n.
0
n = 01
CCS1n
13
1
CCS0n
1: Enables the TOn output operation by counting operation.
1: Outputs a high level from TOn.
0: Sets 0 when TOMn = 0 (master channel output mode).
0: Stops dead time control.
0: Stops real-time output.
1: Enables real-time output.
0: Outputs a low level as real-time output.
1: Outputs a high level as real-time output.
0: Stops modulated output.
0: Stops the TOn output operation by counting operation.
0: Outputs a low level from TOn.
0: Master channel output mode
0: Sets 0 when TOMn = 0 (master channel output mode).
1: Operates as the real-time output trigger generation channel.
Figure 7-63. Example of Set Contents of Registers
12
0
CHAPTER 7 INVERTER CONTROL FUNCTIONS
Count clock selection
TERn
MAS
10B: Selects count clock of master channel.
11
0
Slave/master selection
STSn2
0: Slave channel
10
1
User’s Manual U19678EJ1V1UD
STSn1
9
0
Start trigger selection
STSn0
100B: Selects INTTM00 of master channel.
0
8
CISn1
0
7
CISn0
0
6
Selection of TIn pin input edge
00B: Sets 00B because these are not used.
Operation mode of channel n
0100B: One-count mode
5
0
MDn4
4
0
Start trigger during operation
MDn3
1: Trigger input is valid.
3
1
MDn2
0
2
MDn1
1
0
MDn0
0
1
455

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