UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 922

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remark The special function register (SFR) mounted depend on the product. See 3.2.4 Special function registers
920
Reset function
Low-voltage detector
Regulator
DMA controller
Interrupt
Programmable gain
amplifier amplifier
Comparator
BCD correction circuit
Register
RESF
LVIS
Reset Source
2.
3.
TRAP bit
WDRF bit
INIRF bit
LVIRF bit
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
This value varies depending on the reset source and the option byte.
(SFRs) and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
Cleared (0)
Cleared (0EH)
RESET Input
Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level select register (LVIS)
Regulator mode control register (RMC)
SFR address registers 0, 1 (DSA0, DSA1)
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H)
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H)
Mode control registers 0, 1 (DMC0, DMC1)
Operation control registers 0, 1 (DRC0, DRC1)
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H)
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H)
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 10L,
10H, 11L, 11H, 12L, 12H (PR00L, PR00H, PR01L, PR01H, PR10L,
PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H)
External interrupt rising edge enable register 0 (EGP0)
External interrupt falling edge enable register 0 (EGN0)
Programmable gain amplifier control register (OAM)
Comparator 0 control register (C0CTL)
Comparator 0 internal reference voltage setting register (C0RVM)
Comparator 1 control register (C1CTL)
Comparator 1 internal reference voltage setting register (C1RVM)
BCD correction result register (BCDADJ)
Cleared (0)
Cleared (0EH)
Reset by POC
CHAPTER 19 RESET FUNCTION
Hardware
User’s Manual U19678EJ1V1UD
Set (1)
Held
Held
Held
Cleared (0EH)
Execution of
Instruction
Reset by
Illegal
Held
Set (1)
Held
Held
Cleared (0EH)
Reset by WDT
Held
Held
Set (1)
Held
Cleared (0EH)
Reset by INIRF
00H
0EH
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
Undefined
00H
Acknowledgment
Status After Reset
Note 2
Note 3
Note 2
Held
Held
Held
Set (1)
Held
Reset by LVI
Note 1