UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 853

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol
DMCn
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remark
IFCn
2.
3
0
0
0
0
0
0
0
1
1
1
STGn
<7>
Other than above
n: DMA channel number (n = 0, 1)
44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only.
IFCn
2
0
0
0
1
1
1
1
0
0
1
Figure 16-4. Format of DMA Mode Control Register n (DMCn) (2/2)
IFCn
0
1
0
1
1
0
0
1
1
0
0
DRSn
<6>
IFCn
0
0
0
1
0
1
0
1
0
1
0
INTTM00
INTTM01
INTTM04
INTTM05
INTST0/INTCSI00
INTSR0/INTCSI01
INTST1/INTCSI10/INTIIC10
INTSR1
INTAD
Setting prohibited
CHAPTER 16 DMA CONTROLLER
DSn
After reset: 00H
<5>
User’s Manual U19678EJ1V1UD
Trigger signal
DWAITn
Note 2
Note 2
<4>
−
R/W
Selection of DMA stat source
IFCn3
3
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
End of timer channel 0 count or capture
end interrupt
End of timer channel 1 count or capture
end interrupt
End of timer channel 4 count or capture
end interrupt
End of timer channel 5 count or capture
end interrupt
UART0 transmission transfer end or
buffer empty interrupt/CSI00 transfer end
or buffer empty interrupt
UART0 reception transfer end
interrupt/CSI01 transfer end or buffer
empty interrupt
UART1 transmission transfer end or
buffer empty interrupt/CSI10 transfer end
or buffer empty interrupt/
IIC10 transfer end interrupt
UART1 reception transfer end interrupt
A/D conversion end interrupt
IFCn2
2
Note 1
Trigger contents
Note 2
IFCn1
1
Note 2
IFCn0
0
851