UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 423

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark n = 00, 04
Figure 7-38. Operation Procedure When Triangular Wave PWM Output Function with Dead Time Is Used (2/2)
Operation
stop
TAUS
stop
p = 02, 06
q = 03, 07
The TTn (master), and TTp and TTq (slaves) bits are set
to 1 at the same time.
The TOEn, TOEp, and TOEq bits are cleared to 0 and
values are set to the TOn, TOp, and TOq bits.
To hold the TOn, TOp, and TOq pin output levels
When holding the TOn, TOp, and TOq pin output levels
is not necessary
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
The TTn, TTp, and TTq bits automatically return to 0
because they are trigger bits.
Clears the TOn, TOp, and TOq bits to 0 after the
value to be held is set to the port register.
Switches the port mode register to input mode.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
TEn, TEp, and TEq = 0, and count operation stops.
The TO00, TOp, and TOq pins output the TO00, TOp, and
TOq set levels.
The TOn, TOp, and TOq pin output levels are held by port
function.
The TOn, TOp, and TOq pin output levels go into Hi-Z output
states.
Power-off status
TCRn, TCRp, and TCRq hold count values and stop.
The TOn, TOp, and TOq outputs are not initialized but
hold current statuses.
All circuits are initialized and SFR of each channel is also
initialized.
(The TOn, TOp, and TOq bits are cleared to 0 and the
TOn, TOp, and TOq pins are set to port mode.)
Hardware Status
421