UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 866

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6 Cautions on Using DMA Controller
864
(1) Priority of DMA
Note The short period refers to a period of eight or fewer CPU clocks. The relationship between the lengths of
(2) DMA response time
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. When the requests from either of the
DMA channels are successively generated in a short period
completion of that, the requests from the other DMA channel are executed. In this case, one or tow
instructions are executed between the first DMA transfer and next DMA transfer.
If two DMA requests are generated at the same time, however, DMA channel 0 takes priority over DMA
channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes
precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows.
clock period and DMA operations is as follows.
2 to 4 clock period:
5 to 8 clock period:
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1.
Remark
1 clock period:
Response time
3.
2.
1 clock: 1/f
DMA transfer.
When executing a DMA pending instruction (see 16.6 (4)), the response time is
Do not specify successive transfer triggers for a channel within a period equal
to the maximum response time plus one clock cycle, because they might be
ignored.
The above response time does not include the two clock cycles required for a
extended by the execution time of the instruction to be held pending.
Setting disabled DMA request cannot be accepted.
DMA transfer of the channel where requests are successively generated is
executed.
Whether DMA transfer of the channel where requests are successively generated
is executed or DMA requests from the other channel are executed depends on the
number of times CPU instructions are executed.
Table 16-2. Response Time of DMA Transfer
CLK
CHAPTER 16 DMA CONTROLLER
(f
CLK
3 clocks
User’s Manual U19678EJ1V1UD
: CPU clock)
Minimum Time
Note
10 clocks
, they are successively transferred, and on
Maximum Time
Note