HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 1053

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SSR0—Serial Status Register 0
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
:
:
:
R/(W) *
Transmit Data Register Empty
TDRE
0
1
7
1
[Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
· When the TE bit in SCR is 0
· When data is transferred from TDR to TSR and data can be written to TDR
Note: * RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit
Receive Data Register Full *
0
1
R/(W) *
RDRF
[Clearing conditions]
· When 0 is written to RDRF after reading RDRF = 1
· When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
6
0
in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Overrun Error
0
1
R/(W) *
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1 *
[Setting condition]
When the next serial reception is completed while RDRF = 1 *
5
0
2. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception
Note: * Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Error Signal Status *
cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled.
0
1
R/(W) *
ERS
Data has been received normally, and there is no error signal
[Clearing conditions]
· On reset, or in standby mode or module stop mode
· When 0 is written to ERS after reading ERS = 1
Error signal indicating detection of parity error has been sent by receiving device
[Setting condition]
When the error signal is sampled at the low level
4
0
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Parity Error
0
1
R/(W) *
PER
[Clearing condition]
When 0 is written to PER after reading PER = 1 *
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR *
3
0
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Transmit End
cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled.
0
1
TEND
Transmission in progress
[Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt and writes data to TDR
Transmission has ended
[Setting conditions]
· On reset, or in standby mode or module stop mode
· When the TE bit in SCR is 0 and the ERS bit is 0
· When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after
· When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after
· When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
· When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
2
1
R
transmission of a 1-byte serial character when GM = 0 and BLK = 0
transmission of a 1-byte serial character when GM = 0 and BLK = 1
transmission of a 1-byte serial character when GM = 1 and BLK = 0
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Note: * Retains its previous state when the RE bit in SCR is
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received *
[Setting condition]
When data with a 1 multiprocessor bit is received
1
0
R
cleared to 0 with a multiprocessor format.
Multiprocessor Bit Transfer
0
1
MPBT
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
1
Rev.7.00 Feb. 14, 2007 page 1019 of 1108
2
H'FF7C
1
Appendix B Internal I/O Registers
Smart Card Interface 0
2
REJ09B0089-0700