HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 1087

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TIOR0L—Timer I/O Control Register 0L
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Bit
Initial value
Read/Write
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as
TGR0D I/O Control
:
:
:
:
0
1
IOD3
R/W
7
0
0
1
0
1
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer
the TCNT1 count clock, this setting is invalid and input capture does not
occur.
register, this setting is invalid and input capture/output compare does not
occur.
0
1
0
1
0
1
×
IOD2
R/W
0
1
0
1
0
1
0
1
0
1
×
×
6
0
TGR0D
is output
compare
register
*
TGR0D
is input
capture
register
*
2
2
IOD1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
Note: *
IOD0
TGR0C I/O Control
R/W
0
1
4
0
0
1
0
1
When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer
register, this setting is invalid and input capture/output compare does not
occur.
IOC3
R/W
0
1
0
1
0
1
×
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
0
1
0
1
0
1
0
1
0
1
×
×
TGR0C
is output
compare
register
*
TGR0C
is input
capture
register
*
IOC2
1
R/W
2
0
Rev.7.00 Feb. 14, 2007 page 1053 of 1108
*
1
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
IOC1
R/W
1
0
× : Don't care
H'FFD3
Appendix B Internal I/O Registers
IOC0
R/W
0
0
Input capture at TCNT1 count-up/
count-down
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
REJ09B0089-0700
× : Don't care
TPU0