HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 681

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.14.5 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will
return an undefined value if read, and cannot be modified.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE
0
1
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: Only 0 should be written.
17.14.6 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Description
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
:
:
:
:
—
—
—
—
7
0
7
0
—
—
—
—
6
0
6
0
—
—
—
—
5
0
5
0
—
—
—
—
4
0
4
0
Rev.7.00 Feb. 14, 2007 page 647 of 1108
FLSHE
RAMS
R/W
R/W
3
0
3
0
RAM2
R/W
—
—
2
0
2
0
REJ09B0089-0700
RAM1
Section 17 ROM
R/W
—
—
1
0
1
0
(Initial value)
RAM0
R/W
R/W
—
0
0
0
0