HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 763

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

[7] Initialization
• The general registers other than ER0 and ER1 are saved in the initialization program.
• R0L is a return value of the FPFR parameter.
• Since the stack area is used in the initialization program, a stack area of a maximum 128 bytes
• Interrupts can be accepted during the execution of the initialization program. The program
[8] The return value in the initialization program, FPFR (general register R0L) is judged.
[9] All interrupts and the use of a bus master other than the CPU are prohibited.
[10] FKEY must be set to H'5A and the user MAT must be prepared for programming.
MOV.L #DLTOP+32,ER2
JSR
NOP
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from
(download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization
is executed by using the following steps.
must be saved in RAM.
storage area and stack area in the on-chip RAM and register values must not be destroyed.
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, more
than the specified voltage will be applied and flash memory may be damaged. Therefore,
interrupts and movement of bus mastership to DTC or BREQ other than the CPU are
prohibited.
The interrupt processing prohibition is set up by setting the bit 7 (I) in the condition code
register (CCR) of the CPU to b'1. Then interrupts other than NMI are held and are not
executed.
The NMI interrupts must not occur in the user system.
The interrupts that are held must be processed in executed after all program processing.
When the bus mastership is moved to DTC or BREQ or DRAM refresh except for the CPU,
the error protection state is entered. Therefore, reservation of bus mastership by DTC or BREQ
is prohibited.
@ER2
; Set entry address to ER2
; Call initialization routine
Rev.7.00 Feb. 14, 2007 page 729 of 1108
REJ09B0089-0700
Section 17 ROM