HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 739

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 17.50 Usable Parameters and Target Modes
Name of
Parameter
Download pass/
fail result
Flash pass/fail
result
Flash
programming/
erasing frequency
control
Flash
multipurpose
address area
Flash multi-
purpose data
destination area
Flash erase
block select
Note: * One byte of start address of download destination specified by FTDAR
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the area as much as 4 kbytes starting from the start address specified by
FTDAR. For the address map of the on-chip RAM, see figure 17.69.
The download control is set by using the programming/erasing interface register. The return value
is given by the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the
start address of the on-chip RAM area specified by FTDAR to a value other than the return value
of download (for example, H'FF) before the download start (before setting the SCO bit to 1). Refer
to item [e] in the User Program Mode Programming Procedure portion of section 17.24.2, for
information on the method for checking the download result.
specified by FTDAR)
Abbre-
viation
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
—
—
—
—
—
Down-
load
Initializa-
tion
—
—
—
—
Program-
ming
—
—
—
Rev.7.00 Feb. 14, 2007 page 705 of 1108
Erasure
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
REJ09B0089-0700
Section 17 ROM
Alloca-
tion
On-chip
RAM *
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER0 of
CPU
ER0 of
CPU