HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 110

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 3 MCU Operating Modes
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD
0
1
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
3.2.3
Note: * R/W in the H8S/2319 F-ZTAT.
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2 in the case of the H8S/2319 F-
ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT;
FCCS, FPCS, FECS, FKEY, FMATS, FTDAR, FVARC, FVADRR, FVADRE, FVADRH, and
FVADRL in the case of the H8S/2319C F-ZTAT). For details, see section 17, ROM.
Rev.7.00 Feb. 14, 2007 page 76 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
System Control Register 2 (SYSCR2) (F-ZTAT Versions Only)
Description
PF3 is designated as LWR output pin
PF3 is designated as I/O port, and does not function as LWR output pin
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
—
—
7
0
—
—
6
0
—
—
5
0
—
—
4
0
FLSHE
R/W
3
0
—
—
2
0
—
—
1
0
(Initial value)
(Initial value)
— (R/W) *
—
0
0