HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 633

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note: 7. Write Pulse Width
Note: Use a (z3) μs write pulse for additional
Notes: 1. Data transfer is performed by byte transfer. The lower 8
Number of Writes (n)
Additional program data
Write pulse application subroutine
Reprogram data area
Wait (z1) μs or (z2) μs or (z3) μs
Program data area
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Sub-routine write pulse
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in
4. A 128-byte area for storing program data, a 128-byte area
5. A write pulse of (z1) or (z2) ms should
6. For the values of x, y, z1, z2, z3, α, β, γ,
Clear P bit in FLMCR1
(128 bytes)
(128 bytes)
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
bits of the first address written to must be H'00 or H'80. A
128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be
written to the extra addresses.
the 128-byte programming loop will be subjected to
additional programming if they fail the subsequent verify
operation.
for storing reprogram data, and a 128-byte area for
storing additional program data should be provided in
RAM. The contents of the reprogram
data and additional program data areas
are modified as programming proceeds.
be applied according to the progress of
programming. See note 7 for the pulse
widths. When the additional program
data is programmed, a write pulse of
(z3) μs should be applied. Reprogram
data X' stands for reprogram data to
which a write pulse has been applied.
ε, η, θ, and N, see section 20.3.6, Flash
Memory Characteristics.
Disable WDT
Enable WDT
Wait (α) μs
Wait (y) μs
Wait (β) μs
End sub
Write Time (z) μs
Figure 17.15 Program/Program-Verify Flowchart
*6
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
*6
*5 *6
*6
*6
Increment address
Program Data Operation Chart
Additional Program Data Operation Chart
Reprogram Data (X')
Original Data (D)
0
1
0
1
Verify Data (V)
Verify Data (V)
Store 128-byte program data in program
NG
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
data area and reprogram data area
Transfer additional program data to
Sequentially write 128-byte data in
0
1
0
1
0
1
0
1
Reprogram data computation
additional program data area
(z3) μs additional write pulse
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read data = verify
Read verify data
(z1) μs or (z2) μs
data verification
flash memory
Wait (x) μs
completed?
Write Pulse
Write pulse
Wait (γ) μs
Wait (ε) μs
Wait (η) μs
Wait (θ) μs
data area
Additional Program Data (Y)
128-byte
m = 0?
m = 0
6 ≥ n ?
6 ≥ n ?
data?
n = 1
Start
Reprogram Data (X)
OK
OK
Rev.7.00 Feb. 14, 2007 page 599 of 1108
OK
OK
OK
Sub-routine-call
1
0
1
0
1
NG
NG
NG
NG
*6
*6
*4
*1
See Note *7 for pulse width
*6
*6
*6
*2
*3
*4
*6
*1
*6
*4
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
m = 1
Clear SWE bit in FLMCR1
Programming failure
Perform programming in
the erased state.
Do not perform additional
programming
on previously programmed
addresses.
Wait (θ) μs
Comments
Comments
n ≥ N?
OK
*6
REJ09B0089-0700
Section 17 ROM
NG
n ← n + 1
*6