HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 189

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
6.3.4
Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (sections 6.4, Basic Bus Interface, 6.5, Burst
ROM Interface) should be referred to for further details.
Area 0: Area 0 includes on-chip ROM * , and in ROM-disabled expansion mode, all of area 0 is
external space. In the ROM-enabled expansion mode, the space excluding on-chip ROM * is
external space.
Note: * Applies to mask ROM versions only.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In external expansion mode, all of area 1 to 6 is external space.
When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 to 6.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space .
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7.
Rev.7.00 Feb. 14, 2007 page 155 of 1108
REJ09B0089-0700