HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 175

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Name
Address strobe
Read
High write
Low write
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request
acknowledge
Bus request output
Pin Configuration
Bus Controller Pins
Symbol
AS
RD
HWR
LWR
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
WAIT
BREQ
BACK
BREQO
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Function
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is
to be written, and upper half (D
bus is enabled.
Strobe signal indicating that external space is
to be written, and lower half (D
bus is enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
Strobe signal indicating that area 3 is selected.
Strobe signal indicating that area 4 is selected.
Strobe signal indicating that area 5 is selected.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
Wait request signal when accessing external 3-
state access space.
Request signal that releases bus to external
device.
Acknowledge signal indicating that bus has
been released.
External bus request signal used when internal
bus master accesses external space when
external bus is released.
Rev.7.00 Feb. 14, 2007 page 141 of 1108
Section 6 Bus Controller
REJ09B0089-0700
7
15
to D
to D
0
) of data
8
) of data