HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 738

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 ROM
Bits 6 to 0
TDA6 to
TDA0
H'00
H'01
H'02
H'03
H'04 to H'7F
17.23.2 Programming/Erasing Interface Parameter
The programming/erasing interface parameter specifies the operating frequency, storage place for
program data, programming destination address, and erase block and exchanges the processing
result for the downloaded on-chip program. This parameter uses the general registers of the CPU
(ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a power-on reset or in
hardware standby mode.
When download, initialization, or on-chip program is executed, registers of the CPU except for
ER0 and ER1 are stored. The return value of the processing result is written in R0L. Since the
stack area is used for storing the registers except for ER0 and ER1, the stack area must be saved at
the processing start. (A maximum size of a stack area to be used is 128 bytes.)
The programming/erasing interface parameter is used in the following four items.
(1) Download control
(2) Initialization before programming or erasing
(3) Programming
(4) Erasing
These items use different parameters. The correspondence table is shown in table 17.50.
Here the FPFR parameter returns the results of initialization processing, programming processing,
or erasing processing, but the meaning of the bits differs depending on the type of processing. For
details, refer to the FPFR descriptions for the individual processes.
Rev.7.00 Feb. 14, 2007 page 704 of 1108
REJ09B0089-0700
Description
Download start address is set to H'FFBC00
Download start address is set to H'FFCC00
Download start address is set to H'FFDC00
Download start address is set to H'FFEC00
Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the
download processing.