HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 328

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
8.12.2
Table 8.21 shows the port G register configuration.
Table 8.21 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Port function control register 1
Port function control register 2
Notes: 1. Value of bits 4 to 0.
Port G Data Direction Register (PGDDR)
Bit
Modes 4 and 5
Initial value : Undefined Undefined Undefined
R/W
Modes 6 and 7 *
Initial value : Undefined Undefined Undefined
R/W
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PGDDR is initialized by a reset and in hardware standby mode, to H'10 (bits 4 to 0) in modes
4 and 5, and to H'00 (bits 4 to 0) in modes 6 and 7 * . It retains its prior state in software standby
mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 294 of 1108
REJ09B0089-0700
2. Lower 16 bits of the address.
3. Initial value depends on the mode.
Register Configuration
:
:
:
—
—
—
7
—
—
—
6
Abbreviation
PGDDR
PGDR
PORTG
PFCR1
PFCR2
—
—
—
5
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
W
W
4
1
0
R/W
W
R/W
R
R/W
R/W
W
W
0
0
3
Initial Value *
H'10/H'00 *
H'00
Undefined
H'0F
H'30
W
W
2
0
0
3
1
W
W
1
0
0
Address *
H'FEBF
H'FF6F
H'FF5F
H'FF45
H'FFAC
W
W
0
0
0
2