HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 1093

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TIOR1—Timer I/O Control Register 1
Bit
Initial value
Read/Write
:
:
:
TGR1B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
0
1
×
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
×
×
TGR1B
is output
compare
register
TGR1B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCB1 pin
Capture input
source is TGR0C
compare match/
input capture
TGR1A I/O Control
0
1
IOB0
R/W
4
0
0
1
0
1
×
0
1
0
1
0
1
IOA3
R/W
3
0
×
×
0
1
0
1
0
1
0
1
0
1
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0C compare match/input
capture
TGR1A
is output
compare
register
TGR1A
is input
capture
register
IOA2
R/W
2
0
Rev.7.00 Feb. 14, 2007 page 1059 of 1108
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA1 pin
Capture input
source is TGR0A
compare match/
input capture
IOA1
R/W
1
0
H'FFE2
Appendix B Internal I/O Registers
×
: Don't care
IOA0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
REJ09B0089-0700
×
: Don't care
TPU1