HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 112

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 3 MCU Operating Modes
3.3.3
This is a flash memory boot mode. See section 17, ROM, for details.
Except for the fact that flash memory programming and erasing can be performed, operation in
this mode is the same as in advanced single chip mode.
3.3.4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, ports A, B, and C function as an address bus, ports D and E functions as a data
bus, and part of port F carries bus control signals.
Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output
addresse by setting the corresponding data direction register (DDR) bits and A23E to A20E in
PFCR1 to 1.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if
8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, ports A, B, and C function as an address bus, port D functions as a data bus, and
part of port F carries bus control signals.
Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output
addresses by setting the corresponding data direction register (DDR) bits and A23E to A20E in
PFCR1 to 1.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at
least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16
bits and port E becomes a data bus.
Rev.7.00 Feb. 14, 2007 page 78 of 1108
REJ09B0089-0700
Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)
Mode 4 (Expanded Mode with On-Chip ROM Disabled)
Mode 5 (Expanded Mode with On-Chip ROM Disabled)