HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 322

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
System Control Register (SYSCR)
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in
modes 4 to 6.
Bit 2
LWROD
0
1
Bus Control Register L (BCRL)
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Rev.7.00 Feb. 14, 2007 page 288 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
Description
PF3 is designated as LWR output pin
PF3 is designated as I/O port, and does not function as LWR output pin
Description
External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
External bus release enabled
BRLE
R/W
R/W
—
7
0
7
0
BREQOE
R/W
—
—
6
0
6
0
INTM1
R/W
EAE
R/W
5
0
5
1
INTM0
R/W
R/W
—
4
0
4
1
NMIEG
R/W
R/W
—
3
0
3
1
LWROD
R/W
R/W
—
2
0
2
1
R/W
R/W
—
—
1
0
1
0
(Initial value)
(Initial value)
WAITE
RAME
R/W
R/W
0
1
0
0