HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 845

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.6
19.6.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state or retain the output
state can be specified by the OPE bit in SBYCR. See appendix D, Pin States, for details.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
19.6.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7 * ), or
by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an NMI or IRQ0 to IRQ7 * interrupt request signal is input,
clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable
clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception
handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 * interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7 * is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Note: * Setting the IRQ37S bit to 1 enables IRQ3 to IRQ7 to be used as software standby mode
Clearing with the
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
Clearing with the
hardware standby mode.
clearing sources.
Software Standby Mode
Software Standby Mode
Clearing Software Standby Mode
RES
STBY
Pin: When the RES pin is driven low, clock oscillation is started. At the
Pin: When the STBY pin is driven low, a transition is made to
Rev.7.00 Feb. 14, 2007 page 811 of 1108
Section 19 Power-Down Modes
REJ09B0089-0700