HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 761

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the invalid data to be added is H'FF, the program processing period can be shorted.
[1] Select the on-chip program to be downloaded and the download destination.
[2] Program H'A5 in FKEY
[3] 1 is written to the SCO bit of FCCS and then download is executed.
• RAM emulation mode is canceled.
• H'A5 is written to FKEY.
• The SCO bit writing is executed in the on-chip RAM.
(a) The user-MAT space is switched to the on-chip program storage area.
(b) After the selection condition of the download program and the address set in FTDAR are
(c) The SCO bits in FPCS, FECS, and FCCS are cleared to 0.
(d) The return value is set to the DPFR parameter.
(e) After the on-chip program storage area is returned to the user-MAT space, the user procedure
• In the download processing, the values are stored in the general registers other than ER0 and
When the PPVS bit of FPCS is set to 1, the programming program is selected.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for download
request.
To write 1 to the SCO bit, the following conditions must be satisfied.
When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned
to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of the DPFR parameter. Before
the SCO bit is set to 1, incorrect judgement must be prevented by setting the DPFR parameter,
that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value
other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
checked, the transfer processing is executed starting from the on-chip RAM address specified
by FTDAR.
program is returned.
ER1of the CPU.
Rev.7.00 Feb. 14, 2007 page 727 of 1108
REJ09B0089-0700
Section 17 ROM