HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 473

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode and with a
multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit
setting.
Bit 5
PE
0
1
Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when
parity addition and checking is disabled in asynchronous mode.
Bit 4
O/E
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bits setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/E bit.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
2
1
Section 12 Serial Communication Interface (SCI)
Rev.7.00 Feb. 14, 2007 page 439 of 1108
REJ09B0089-0700
(Initial value)
(Initial value)