HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 760

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 ROM
Programming Procedure in User Program Mode: The procedures for download, initialization,
and programming are shown in figure 17.70.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 17.29.3, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
Rev.7.00 Feb. 14, 2007 page 726 of 1108
REJ09B0089-0700
set download destination
JSR FTDAR setting+32
Select on-chip program
to be downloaded and
Set the FPEFEQ and
FUBRA parameters
procedure program
Set SCO to 1 and
execute download
Start programming
Set FKEY to H'A5
Clear FKEY to 0
Initialization
DFPR=0?
FPFR=0?
by FTDAR
1
Yes
Yes
Initialization error processing
Download error processing
Figure 17.70 Programming Procedure
No
No
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
No
ER1 (FMPAR and FMPDR)
Disable interrupts and bus
Set parameter to ER0 and
JSR FTDAR setting+16
master operation other
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
programming is
Programming
Required data
completed?
FPFR=0?
than CPU
1
Yes
Yes
Clear FKEY and
error processing
No
programming
(i)
(j)
(k)
(l)
(m)
(n)
(o)