HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 318

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
8.11.2
Table 8.19 shows the port F register configuration.
Table 8.19 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Bus control register L
System control register
Port function control register 1
Port function control register 2
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
Bit
Modes 4 to 6 *
Initial value :
R/W
Mode 7 *
Initial value :
R/W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6 * , and to
H'00 in mode 7 * . It retains its prior state in software standby mode. The OPE bit in SBYCR is
used to select whether the bus control output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 284 of 1108
REJ09B0089-0700
2. Initial value depends on the mode.
Register Configuration
:
:
:
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
W
W
7
1
0
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
BCRL
SYSCR
PFCR1
PFCR2
W
W
5
0
0
W
W
4
0
0
R/W
W
R/W
R
R/W
R/W
R/W
R/W
W
W
0
0
3
Initial Value
H'80/H'00 *
H'00
Undefined
H'3C
H'01
H'0F
H'30
W
W
2
0
0
2
W
W
1
0
0
Address *
H'FEBE
H'FF6E
H'FF5E
H'FED5
H'FF39
H'FF45
H'FFAC
W
W
0
0
0
1