HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 320

IC H8S MCU FLASH 256K 100-QFP

HD64F2318VTE25

Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of HD64F2318VTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Section 8 I/O Ports
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For
details, see section 8.12, Port G.
Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For
details, see section 8.12, Port G.
Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output.
This bit is valid in modes 4 to 6.
Bit 5
PF1CS5S
0
1
Bit 4—Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output.
This bit is valid in modes 4 to 6.
Bit 4
PF0CS4S
0
1
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). For details, see
section 8.2, Port 1.
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). For details, see
section 8.2, Port 1.
Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see
section 8.2, Port 1.
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see
section 8.2, Port 1.
Rev.7.00 Feb. 14, 2007 page 286 of 1108
REJ09B0089-0700
Description
PF1 is the PF1/BACK/IRQ1 pin
PF1 is the PF1/BACK/IRQ1/CS5 pin. CS5 output is enabled when BRLE = 0,
CS25E = 1, and PF1DDR = 1
Description
PF0 is the PF0/BREQ/IRQ0 pin
PF0 is the PF0/BREQ/IRQ0/CS4 pin. CS4 output is enabled when BRLE = 0,
CS25E = 1, and PF0DDR = 1
(Initial value)
(Initial value)

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