HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 288

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
8.6.2
Table 8.9 shows the port A register configuration.
Table 8.9
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: 1. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit
Initial value : Undefined Undefined Undefined Undefined
R/W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are
reserved.
PADDR is initialized to H'0 (bits 3 to 0) by a reset and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
• Modes 4 and 5
• Mode 6 *
Rev.7.00 Feb. 14, 2007 page 254 of 1108
REJ09B0089-0700
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
Setting PADDR bits to 1 makes the corresponding port A pins address outputs, while clearing
the bits to 0 makes the pins input ports.
2. Lower 16 bits of the address.
Register Configuration
:
:
Port A Registers
—
—
7
—
—
6
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
—
—
5
—
—
4
R/W
W
R/W
R
R/W
R/W
PA3DDR PA2DDR PA1DDR PA0DDR
W
0
3
Initial Value *
H'0
H'0
Undefined
H'0
H'0
W
2
0
1
W
1
0
Address *
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
W
0
0
2