HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 632

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

reprogramming is necessary, set program mode again, and repeat the program/program-verify
sequence as before. However, ensure that the program/program-verify sequence is not repeated
more than (N) times on the same bits.
Section 17 ROM
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 + α + β) μs as the WDT overflow period. After this, preparation
for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the
elapse of (y) μs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the
programming time according to the table in the programming flowchart.
17.7.2
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) μs later). Next, the watchdog
timer is cleared after the elapse of (β) μs or more, and the operating mode is switched to program-
verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) μs or more. When the flash memory is read in this state (verify data
is read in 16-bit units), the data at the latched address is read. Wait at least (ε) μs after the dummy
write before performing this read operation. Next, the originally written data is compared with the
verify data, and reprogram data is computed (see figure 17.15) and transferred to the reprogram
data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least
(η) μs, then clear the SWE bit in FLMCR1 to 0, and wait again for at least (θ) μs. If
Rev.7.00 Feb. 14, 2007 page 598 of 1108
REJ09B0089-0700
Program-Verify Mode