HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 330

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
Port Function Control Register 1 (PFCR1)
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. Change
the CSS17 bit setting only when the corresponding DDR bit is 0. This bit is valid in modes 4 to 6.
Bit 7
CSS17
0
1
Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. Change
the CSS36 bit setting only when the corresponding DDR bit is 0. This bit is valid in modes 4 to 6.
Bit 6
CSS36
0
1
Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Enables or disables CS5 output. For details,
see section 8.11, Port F.
Bit 4—Port F0 Chip Select 4 Select (PF0CS4S): Enables or disables CS4 output. For details,
see section 8.11, Port F.
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). For details, see
section 8.2, Port 1.
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). For details, see
section 8.2, Port 1.
Rev.7.00 Feb. 14, 2007 page 296 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
:
:
Description
PG3 is the PG3/CS1 pin. CS1 output is enabled when CS167E = 1 and PG3DDR =
1
PG3 is the PG3/CS7 pin. CS7 output is enabled when CS167E = 1 and PG3DDR =
1
Description
PG1 is the PG1/IRQ7/CS3 pin. CS3 output is enabled when CS25E = 1 and
PG1DDR = 1
PG1 is the PG1/IRQ7/CS6 pin. CS6 output is enabled when CS167E = 1 and
PG1DDR = 1
CSS17
R/W
7
0
CSS36 PF1CS5S PF0CS4S
R/W
6
0
R/W
5
0
R/W
4
0
A23E
R/W
3
1
A22E
R/W
2
1
A21E
R/W
1
1
(Initial value)
(Initial value)
A20E
R/W
0
1