HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 27

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.2 Register Descriptions ........................................................................................................ 535
14.3 Interface to Bus Master ..................................................................................................... 540
14.4 Operation........................................................................................................................... 541
14.5 Interrupts ........................................................................................................................... 547
14.6 Usage Notes ...................................................................................................................... 548
Section 15 D/A Converter..................................................................................553
15.1 Overview........................................................................................................................... 553
15.2 Register Descriptions ........................................................................................................ 556
15.3 Operation........................................................................................................................... 559
Section 16 RAM ................................................................................................561
16.1 Overview........................................................................................................................... 561
16.2 Register Descriptions ........................................................................................................ 562
16.3 Operation........................................................................................................................... 563
16.4 Usage Note........................................................................................................................ 563
Section 17 ROM ................................................................................................565
17.1 Overview........................................................................................................................... 565
14.1.3 Pin Configuration................................................................................................. 533
14.1.4 Register Configuration......................................................................................... 534
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 535
14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 536
14.2.3 A/D Control Register (ADCR) ............................................................................ 538
14.2.4 Module Stop Control Register (MSTPCR) .......................................................... 539
14.4.1 Single Mode (SCAN = 0) .................................................................................... 541
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 543
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 545
14.4.4 External Trigger Input Timing ............................................................................. 546
15.1.1 Features................................................................................................................ 553
15.1.2 Block Diagram ..................................................................................................... 554
15.1.3 Pin Configuration................................................................................................. 555
15.1.4 Register Configuration......................................................................................... 555
15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ....................................................... 556
15.2.2 D/A Control Registers 01 (DACR01) .................................................................. 556
15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 558
16.1.1 Block Diagram ..................................................................................................... 561
16.1.2 Register Configuration......................................................................................... 562
16.2.1 System Control Register (SYSCR) ...................................................................... 562
17.1.1 Block Diagram ..................................................................................................... 565
Rev.7.00 Feb. 14, 2007 page xxv of xxxii
REJ09B0089-0700