HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 940
HD64F2318VTE25
Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2318VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Appendix A Instruction Set
A.4
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A.4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as follows:
Examples: Advanced mode, program code, and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
2. JSR @@30
Rev.7.00 Feb. 14, 2007 page 906 of 1108
REJ09B0089-0700
From table A.5:
I = L = 2, J = K = M = N = 0
From table A.4:
S
Number of states required for execution = 2 × 4 + 2 × 2 = 12
From table A.5:
I = J = K = 2, L = M = N = 0
From table A.4:
S
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Execution states = I × S
I
I
= 4, S
= S
J
Number of States Required for Instruction Execution
= S
L
K
= 2
= 4
I
+ J × S
J
+ K × S
K
+ L × S
L
+ M × S
M
+ N × S
N
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