HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 244

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Data Transfer Controller
7.3.11
Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
[5] After the end of one data transfer, or after the specified number of data transfers have ended,
Activation by Software: The procedure for using the DTC with software activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0.
[4] Write 1 to the SWDTE bit and the vector number to DTVECR.
[5] Check the vector number written to DTVECR.
[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
Rev.7.00 Feb. 14, 2007 page 210 of 1108
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is activated when an interrupt used as an activation source is generated.
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
Procedures for Using DTC