HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 619

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.5.3
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a
read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 17.7.
17.5.4
Notes: 1. Available only in the H8S/2315 F-ZTAT and H8S/2314 F-ZTAT.
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0, bits 7 to 2 are reserved in the H8S/2317
F-ZTAT). Bits 7 to 4 are reserved (bits 7 and 6 are reserved in the H8S/2315 F-ZTAT and
H8S/2314 F-ZTAT): they are always read as 0 and cannot be modified. When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 17.7.
Bit
EBR1
Initial value :
R/W
Bit
EBR2
Initial value :
R/W
2. Reserved in the H8S/2317 F-ZTAT. Only 0 should be written.
Erase Block Register 1 (EBR1)
Erase Block Register 2 (EBR2)
:
:
:
:
R/W
EB7
—
—
7
0
7
0
R/W
EB6
—
—
6
0
6
0
EB13 *
R/W *
R/W
EB5
5
0
5
0
1
1
EB12 *
R/W *
EB4
R/W
4
0
4
0
1
1
Rev.7.00 Feb. 14, 2007 page 585 of 1108
EB11 *
R/W
R/W
EB3
3
0
3
0
2
EB10 *
R/W
R/W
EB2
2
0
2
0
2
REJ09B0089-0700
Section 17 ROM
R/W
R/W
EB1
EB9
1
0
1
0
EB0
R/W
EB8
R/W
0
0
0
0