HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 360

• Manufacturer Part Number: HD64F2318VTE25
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2318VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 16-Bit Timer Pulse Unit (TPU)
Channel
1
Channel
2
Rev.7.00 Feb. 14, 2007 page 326 of 1108
REJ09B0089-0700
Bit 3
IOA3
Bit 3
IOA3
0
1
0
1
Bit 2
IOA2
0
1
0
1
Bit 2
IOA2
0
1
×
Bit 1
IOA1
0
1
0
1
0
1
×
Bit 1
IOA1
0
1
0
1
0
1
Bit 0
IOA0 Description
0
1
Bit 0
IOA0 Description
0
1
0
1
0
1
1
0
0
1
×
×
0
1
0
1
1
0
0
1
×
TGR1A
is output
compare
register
TGR1A
is input
capture
register
TGR2A
is output
compare
register
TGR2A
is input
capture
register
Output disabled
Output disabled
Output disabled
Initial output is 0
output
Initial output is 1
output
Capture input
source is
TIOCA1 pin
Capture input
source is TGR0A
compare match/
input capture
Output disabled
Initial output is 0
output
Initial output is 1
output
Capture input
source is
TIOCA2 pin
match
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare
match/input capture
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
(Initial value)
(Initial value)
×: Don’t care
×: Don’t care