L64105 LSI Logic Corporation, L64105 Datasheet - Page 103

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.22
7
Reserved
Register 69 (0x045)
Enable Video Read Compare DTS
Enable Audio Read Compare DTS [1:0]
Video Decoder Registers
5
Video Numitems/Pics Panic
When this bit is set, the Video ES channel buffer read
pointer is compared with the Video ES Channel Buffer
Compare DTS Address written in Registers 108, 109,
and 110
addresses match, the DTS Video Event Interrupt bit
(Register 2, bit 7,
generated, if not masked, by asserting the INTRn output
signal. This can be used as an aid to audio/video
synchronization by the host software. When INTRn is
asserted, the host should read Registers 0 through 4 to
determine the cause of the interrupt, take the necessary
action, and deassert INTRn by setting the Clear Interrupt
Pin bit (Register 6, bit 0,
The bit encoding and meanings are shown in the
following table.
Bits
0b00
0b01
0b10
0b11
When these bits are configured for a compare, the
selected Audio ES channel buffer read pointer is
compared with the Audio ES Channel Buffer Compare
DTS Address written in Registers 111, 112, and 113
(page
the DTS Audio Event Interrupt bit (Register 2, bit 6,
page
masked, by asserting the INTRn output signal. This can
be used as an aid to audio/video synchronization by the
host software.
4
Mode Select
4-6) is set and an interrupt is generated, if not
4-28) by the host. When the two addresses match,
Description
Disable compare
Audio decoder read pointer compare
IEC958 (S/P DIF) read pointer compare
Reserved
(page
3
4-27) by the host. When the two
page
4-6) is set and an interrupt is
Enable Audio Read
page
2
Compare DTS
4-10).
1
Read Compare
Enable Video
R/W [2:1]
DTS
0
R/W 0
4-21