L64105 LSI Logic Corporation, L64105 Datasheet - Page 166

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.126 Register 362 (0x16A) PCM Scale [7:0]
Figure 4.127 Register 363 (0x16B)
4-84
Valid
7
7
User
6
This is an 8-bit, fractional, scale factor for scaling output PCM. PCM
Scale = 0x00 mutes the audio output; PCM Scale = 0xFF keeps the
output PCM scaled as decoded. Intermediate values (0x01, ..., 0xFE)
scale the output PCM by factors of 2/256 to 255/256.The default value
of this register is 0xFF.
ACLK Select[1:0]
Invert LRCLK
Reserved
Register Descriptions
5
These bits select the external audio clock used for
generating the DAC and S/P DIF clocks. Note that N in
the table below stands for 768, 512, 384, or 256
according to the ACLK_ multiple(s) provided. See also
the ACLK Divider Select bits, bits [3:0] in Register 364.
ACLK Select
0b00
0b01
0b10
0b11
The default value is 0b01 (48 kHz).
The audio LRCLK output signal polarity indicates to the
external audio DAC to which channel, left or right, the
current audio sample belongs. The default setting of this
bit is 0 which means that right samples are output when
LRCLK is high and left samples are output when LRCLK
is low. Setting this bit inverts the LRCLK sense. Set or
clear this bit according to the requirements of your audio
DAC.
Clear these bits when writing to this register.
Reserved
PCM Scale [7:0]
R/W
External Clock Used
ACLK_441 (44.1 kHz * N)
ACLK_48 (48 kHz * N)
ACLK_32 (32 kHz * N)
Reserved
3
Invert LRCLK
2
ACLK Select [1:0]
1
R/W [1:0]
R/W 2
0
0
[5:3]